Embodiments of the present invention relate to a method for manufacturing a semiconductor device in which a capacitor structure is modified to ensure capacitance of the capacitor, and the height of the capacitor is reduced to prevent the leaning capacitor or a defective or poor bridge from being generated, such that the fabrication process of semiconductor devices is simplified and therefore the semiconductor devices can be stably manufactured.
In case of a semiconductor device such as a Dynamic Random Access Memory (DRAM), it is necessary to reduce the area occupied by the semiconductor device in proportion to the increasing degree of integration while maintaining or increasing the level of electrostatic capacitance. There are a variety of methods to guarantee sufficient cell electrostatic capacitance within a limited area; for example, using a high dielectric material as a dielectric film, reducing a thickness of the dielectric film, increasing an effective region of a lower electrode, etc. However, using the high dielectric material requires time and material investment, for example, the introduction of new equipment or installations, the necessity of verifying the reliability and productivity of a dielectric film, low-temperature processing of a subsequent process, etc. Accordingly, increasing the effective region has an advantage in that a conventional dielectric film can be continuously used and the implementation of a fabrication process becomes relatively easier. Increasing the effective region has been widely used in the actual fabrication process due to the above-mentioned advantages.
There are a variety of known methods to increase an effective region of the lower electrode, for example, a method for configuring a lower electrode in the form of a three-dimensional (3D) structure (such as a cylinder or a fin), a method for growing a Hemi Spherical Grain (HSG) on a lower electrode, a method for increasing the height of a lower electrode, etc. Specifically, the method for growing the HSG may cause unexpected problems in guaranteeing a Critical Dimension (CD) of at least a predetermined level between lower electrodes, and may cause a bridge between lower electrodes due to infrequent HSG desquamation, so that it is difficult for the aforementioned HSG growing method to be applied to a semiconductor device based on a design rule of 0.14 μm or less. Therefore, in general, in order to increase cell electrostatic capacitance, a variety of methods for configuring a lower electrode in the form of a 3D structure and increasing the height of the lower electrode have been widely used. A representative example of such methods is a method for forming a cylindrical lower electrode or a stack-shaped lower electrode.
Specifically, conventional methods for forming the cylindrical lower electrode necessarily include removing a sacrificial insulation film from a peripheral part of the lower electrode, and depositing a dielectric film over the lower electrode. In this case, the dielectric material contained in the dielectric film is not deposited only over the lower electrode, but is deposited between neighboring lower electrodes, such that all the cells can share a dielectric material and an upper electrode formed over the dielectric material. Provided that the cells share and use such a dielectric material, capacitance (storage capacitance) among all the lower electrodes may be interfered or distorted.
As described above, in order to maximize cell capacitance for improving refresh characteristics of the conventional cylindrical lower electrode, the height of each lower electrode becomes increased and the spacing between the lower electrode contact plugs is smaller. As a result, there arises a bridge between lower electrodes, and it is difficult to guarantee a contact region between the lower electrode contact plug and the lower electrode.